1. Field of the Invention
The present invention relates to an information processing apparatus that controls memory access according to a priority of transfer and a memory controller memory control circuit, and a control method thereof.
2. Description of the Related Art
In recent years, a memory system in which a plurality of masters shares one memory via an on-chip bus has been mainly used. In such a system, each master asynchronously issues transfer. However, each master performs various types of transfers, for example, a certain latency should be satisfied, or a certain transmission band should be satisfied. The transfer requiring guarantee of the latency is treated as a high-priority transfer, and various types of methods are provided for processing the high-priority transfer earlier than other transfers.
For example, Japanese Patent Application Laid-Open No. 2011-165105 discusses a method in which a memory control circuit provides a transfer queue requiring calculation of latency and a transfer queue not requiring it, and determines, depending on a status, which transfer instruction held by queues is to be taken to access a memory. Further, Japanese Patent Application Laid-Open No. 2006-250555 discusses a method in which a queue holding the transfer is provided for each address region to which the memory control circuit access, and performs a memory accesses from the high-priority transfer of the queue in an access region.
In a case where a transfer unit from the on-chip bus to the memory control circuit is different from the transfer unit from the memory control circuit to the memory, the transfer from the on-chip bus is required to be divided and adjusted. More specifically, to realize the transfer of one transfer unit from the on-chip bus, the memory control circuit is required to issue a plurality of memory access commands.
However, in the methods discussed in Japanese Patent Application Laid-Open No. 2011-165105 and Japanese Patent Application Laid-Open No. 2006-250555, the methods are not configured to be capable of taking into account the priority of the memory access that is divided and issued. Therefore, if a memory access request having a low priority is received from the on-chip bus and divided into a plurality of memory access commands, even if another memory access request having the high priority is received, until the memory access is completed based on the plurality of memory access commands generated from the memory access request having the low priority, processing on the memory access request having the high priory cannot be started.
For example, 8-beat transfer is performed from the on-chip bus and it is divided into two memory access commands, and four cycles are required to access a memory. Since the two memory accesses are continuously processed, subsequent transfer is not processed during eight cycles. On the other hand, if 128-beat transfer is performed from the on-chip bus, it is divided into 32 memory accesses. If each requires four cycles, the subsequent transfer is not processed during 128 cycles. As described above, even if the subsequent transfer has the high priority, another transfer cannot be processed while the divided memory accesses are executed, and thus the transfer having the high priority does not have a high transfer efficiency.